1. Field of the Invention
The present invention relates to a subchannel memory access control system in a data processing system having at least one block multiplexor channel connected to at least one input/output (I/O) control unit of a first type which controls, in parallel and on a time-shared basis, a plurality of input/output devices, and at least one other block multiplexor channel connected to at least one input/output control unit of a second type which controls another plurality of input/output devices on a non-time shared basis wherein only one control unit is operated at a time. Unit control word (UCW) memory domains (i.e., areas within the subchannel memory for storing unit control words) are pooled for use, on an unshared basis, by operational input/output devices of the first mentioned type of input/output control unit, while the input/output devices controlled by the second mentioned type of input/output control unit use in common or share the unit control word memory domains provided on a one-to-one basis with respect to each second mentioned type of input/output control unit. Furthermore, access to both unshared and shared unit control word memory domains is achieved by use of information stored in a separately provided assign table memory domain (i.e., an area within the subchannel memory in which is stored a table defining which UCW memory domain is assigned to which I/O control unit).
Generally, an input/output device is controlled by an input/output control unit, while the input/output control unit is controlled by a central processing unit (CPU) via a channel unit. In the central processing unit, predetermined processing is performed by using the unit control word of the main memory for respective operation requests from each input/output device and for an operation request from the central processing unit to the input/output device under the control of a program in the CPU.
2. Description of the Prior Art
Conventionally, memory domains for a unit control word have been provided one-to-one correspondence with the number of input/output devices. For example, when it is desired that each input/output control unit be capable of connection to as many as m input/output devices, each channel unit can be connected with as many as n input/output control units and a total of k channel units can be connected to make up a whole system. Therefore, k .times. m .times. n memory domains (this is called the subchannel memory) for storing said unit control words have to be provided. In practice, however, there is no case where the input/output devices numbering k .times. m .times. n are all connected to the system and ready for use at the same time. The n input/output control units are rarely respectively connected to every channel unit even if a total of k channel units are connected to the system. In some cases, n input/output control units are connected to specific channels. However, even in those cases, less than n input/output control units are connected to the other channels. Also, m input/output devices are rarely connected to every one of the n input/output control units. Generally, of the input/output devices, less than half of the k .times. m .times. n devices are ever connected at any one time. Therefore, it will be sufficient for the subchannel memory to reserve the memory domains for unit control words to, at most, half of k .times. m .times. n.
In general, however, each input/output device accesses a unit control word of the UCW memory domain according to the device number assigned to the I/O device. The device number consists of the corresponding channel number (0 to k-1), input/output control number (0 to n-1), and the input/output device number (0 to m-1). It is to be noted that the device number will be skipped when devices less in number than that maximum number allowed according to the specification are connected to the system. On the other hand, it is desirable, and even necessary, that the memory domain used for providing the unit control words for subchannel memory be continuous. That is to say, if a device number is skipped, and thus the corresponding address in the UCW memory is skipped, the usage of the UCW memory domains will be discontinuous, deteriorating the utilization and access efficiency of the memory. Moreover, the channel units and the input/output control units can respectively be classified into several types. For instance, channel units can be classified into a byte multiplexor channel (hereinafter referred to as multiplexor channel, MXC) and a block multiplexor channel (BMC). For the multiplexor channel unit (MXC), each time the channel performs a data transfer for one byte, it is disconnected from the interface in order to check to see if another channel unit is issuing a request for data transfer. If such a request is not issued, the relevant channel unit continues the data transfer of the next byte. In the case of the BMC, the data transfer is controlled for every block (several tens to several hundred bytes) in the same manner as mentioned above.
The input/output control units can be classified into those (hereinafter referred to as the input/output control unit of the 1st group) which are connected to the multiplexor channel MXC and control the input/output devices having comparatively low speed operation such as card readers, card punchers, and line printers, etc.; those (hereinafter referred to as the input/output control unit of the 2nd group) which are connected to the block multiplexor channel BMC and control the input/output devices having comparatively high speed operation such as magnetic disk units, magnetic drum units, etc. in which the same device operates for, at most, only a few blocks at a time; and those (hereinafter referred to as the input/output control unit of the 3rd group) which are also connected to the block multiplexor channel BMC and control the input/output devices such as magnetic tape units in which the same device often operates for several hundred blocks successively.
There is no need to provide a unit control word (UCW); domain for each input/output device of an input/output control unit of the 3rd group, since it will be sufficient to provide them as corresponding to each input/output control unit. However, in the case where the input/output control unit is of the 2nd group, it is inconvenient to provide only one unit control word domain corresponding to each input/output control unit, since two or more input/output devices are controlled in some cases on a time sharing basis and data transfer is performed one block at a time; thus two or more devices are virtually operated in parallel for several blocks. Therefore, for control units and related devices of the second group, it is desirable to provide a pool of UCW domains for selective use by those devices in operation with control units of the second group.